What problems does impedance mismatch actually cause in high-speed PCB design?

Anyone who has designed high-speed PCBs has likely encountered this situation: the schematic is correct, the PCB layout is accurate, but once the board is assembled and powered up—something’s wrong. Signal waveforms have glitches, timing is off, there are occasional bit errors, and in severe cases, the system won’t even boot up.

After hours of troubleshooting—with the power supply and clock signals both confirmed to be fine—you finally discover that the trace impedance wasn’t controlled properly.

Impedance mismatch is one of the most common issues in high-speed design, yet it’s a pitfall that many people tend to overlook. 

This article clearly explains the problems caused by impedance mismatch, their causes, and the solutions.

I. First, Let’s Clarify: What Is Impedance Mismatch?

Simply put, it’s when a signal encounters an “obstacle” during transmission.

When a signal travels along a PCB trace, it is essentially propagating along a transmission line. A transmission line has a characteristic impedance, which depends on the trace’s geometric dimensions (line width, spacing, and dielectric thickness) and the dielectric material.

When the source impedance, transmission line impedance, and load impedance are all equal, the signal energy is transmitted completely without reflection. This is known as impedance matching.

However, reality often doesn’t work this way. Changes in layer, variations in trace width, via interruptions, or missing termination resistors—all of these can cause impedance discontinuities, resulting in impedance mismatch.

1. Why Does Impedance Mismatch Occur?

There are several common causes:

Trace Width Variations:

When a trace narrows or widens, the impedance changes. For example, when fanning out from a chip pin, the trace starts very narrow and widens toward the center, resulting in impedance discontinuity.

Layer Changes:

When a signal transitions from one layer to another, vias can introduce impedance discontinuities. If the transition between reference planes is not properly handled during layer changes, the problem becomes more severe.

Changes in the reference plane:

If the reference plane beneath the signal trace is incomplete—for example, due to cross-splits or excessive vias—the impedance will change abruptly.

Improper termination:

If there is no appropriate terminating resistor at the source or load end, impedance mismatch occurs directly at the endpoints.

2. What is the fundamental cause of impedance mismatch?

The fundamental cause is reflection.

When a signal is transmitted to a point of impedance discontinuity, part of the energy continues to propagate forward, while another part is reflected back. The reflected signal superimposes with the incident signal, causing signal waveform distortion.

The magnitude of the reflection is measured by the reflection coefficient:

Reflection coefficient Γ = (ZL - Z0) / (ZL + Z0)

Where ZL is the load impedance and Z0 is the characteristic impedance of the transmission line. When ZL = Z0, the reflection coefficient is 0, and there is no reflection.

The greater the difference between the two, the more severe the reflection.

II. What Problems Does Impedance Mismatch Cause?

Ultimately, all problems caused by impedance mismatch stem from reflections. Specific manifestations include the following:

1. Signal Overshoot and Undershoot

This is the most obvious manifestation. The reflected signal superimposes on the original signal, causing the signal to overshoot beyond the power supply voltage or undershoot below ground potential during transitions.

What are the dangers of overshoot? At best, signal quality deteriorates; at worst, it can damage the chip’s input pins. 

This is particularly true for modern low-voltage differential signals, where overshoot exceeding a few hundred millivolts can cause problems.

Undershoot poses an even greater risk. If the signal drops below ground potential, it may cause the internal PN junction of the chip to become forward-biased, triggering a latch-up effect—which, in severe cases, can directly destroy the chip.

2. Ringing and Glitches

Reflected signals bounce back and forth multiple times between the source and load, causing the signal to oscillate around the target level—this is known as ringing.

Ringing causes the signal to oscillate back and forth during level transitions, prolonging the settling time. For designs with tight timing constraints, ringing can lead to insufficient timing margins.

Glitches are easier to understand. Brief pulses generated by the superposition of reflections may be misinterpreted as signal transitions, resulting in logic errors.

3. Signal Timing Degradation

Reflections do not simply vanish; they propagate back and forth along the transmission line, consuming time.

Signal settling, which could originally be completed within a single clock cycle, takes longer due to reflections,

eroding timing margins. In high-speed designs, nanosecond-level timing margins can be completely consumed by reflections. 

What’s more, the delay of reflections is related to trace length and the dielectric constant of the material, making it difficult to accurately predict during the design phase.

 Often, insufficient timing margins are only discovered after the board is manufactured and tested.

4. Increased Bit Error Rate

For high-speed serial signals (such as PCIe, SATA, and USB), impedance mismatch causes the eye diagram to close, resulting in an increased bit error rate.

The eye diagram is a visual representation of signal quality. Signals with good impedance matching exhibit a wide eye opening and low jitter. 

When impedance is mismatched, reflections cause the eye diagram to close, increasing signal jitter near the sampling points and raising the probability of errors.

Once the bit error rate rises, system stability is compromised. Many instances of occasional packet loss, system crashes, and reboots are caused by bit errors in high-speed signals.

5. Increased EMI Radiation

This is something many people do not consider. Reflections caused by impedance mismatch essentially mean that energy is not fully absorbed by the load. 

Where does this energy go? Part of it is reflected back to the source, while the rest is radiated outward as electromagnetic waves.

The more severe the reflection, the greater the radiated energy. 

Combined with the inherently high frequencies of high-speed signals, which result in higher radiation efficiency, exceeding EMI test limits is a common occurrence.

III. How to Determine Impedance Matching

Determining impedance matching can be approached from two angles: the design phase and the testing phase.

1. Design Phase

Most modern EDA tools support impedance calculation and verification.

Impedance Calculation: Based on the layer stackup and material parameters, calculate the characteristic impedance corresponding to different trace widths. 

Ensure that the trace impedance meets the requirements (typically 50Ω for single-ended and 100Ω for differential).

Impedance Check: Many tools support DRC checks to identify locations of impedance discontinuities.

 These include trace layer changes, variations in trace width, and breaks in the reference plane, all of which are flagged.

However, tools can only detect problems; they cannot resolve them. The key is to consciously avoid impedance discontinuities during the design phase.

2. Testing Phase

Once the board is fabricated, impedance can be measured using a TDR (Time Domain Reflectometer).

The TDR sends a fast-rising-edge pulse while simultaneously measuring the reflected signal. 

Based on the position and amplitude of the reflected signal, it is possible to determine where impedance discontinuities occur and by how much they deviate.

An oscilloscope can also observe typical symptoms of impedance mismatch: overshoot, undershoot, and ringing. However, these are merely surface-level indicators; pinpointing the exact location still requires a TDR.

IV. How to Resolve Impedance Mismatch Issues

The core of resolving impedance mismatch is ensuring impedance continuity. Specific measures include the following:

1. Termination Resistors

This is the most direct method. By adding termination resistors at the signal source or load end, the termination impedance is made equal to the transmission line’s characteristic impedance. 

Common termination methods include source-side series termination, load-side parallel termination, and Thevenin termination. 

Source-side series termination is suitable for point-to-point signals, where a resistor is connected in series with the source output to absorb reflections. 

Terminal parallel termination is suitable for multi-point buses; the resistor is connected in parallel at the load end to match the transmission line impedance. 

The selection and placement of termination resistors are critical. 

The resistance value must be precise, and the resistor should be placed close to the end point. The farther it is from the end point, the poorer the termination effect.

2. Controlling Trace Geometric Parameters

Trace impedance is primarily determined by trace width, trace spacing, and dielectric thickness. During design, consistency in these parameters must be ensured.

Avoid abrupt changes in trace width: If trace width must be altered, use a gradual transition; do not change directly from wide to narrow.

Add ground vias when changing layers: When a signal crosses a layer boundary, place a ground via next to the signal via to ensure the continuity of the reference plane.

Avoid crossing planes: High-speed signals must never cross the boundary between power and ground planes. Crossing these boundaries will cause a break in the reference plane and an abrupt change in impedance.

3. Optimizing Stackup Design

The stackup design significantly affects impedance. The closer the signal layer is to the reference plane, the easier it is to control impedance, and the stronger the immunity to interference.

High-speed signals should be routed adjacent to a continuous ground plane. 

The selection of stackup materials is also critical. Materials with different dielectric constants result in different impedances for the same geometric dimensions.

Verify the board material parameters before design and use accurate dielectric constants when calculating impedance.

4. Simulation Verification

Simulation is indispensable in high-speed design.

Signal integrity simulation can identify locations of impedance discontinuities during the design phase, allowing issues to be avoided in advance. 

Simulation tools can calculate trace impedance, predict reflection waveforms, and evaluate the effectiveness of termination schemes.

The accuracy of the simulation depends on the precision of the model. Input data such as the chip’s IBIS model and the PCB’s stack-up parameters must be accurate for the simulation results to be meaningful.

V. Summary

Impedance mismatch is one of the most common issues in high-speed design, and its consequences include:

Signal overshoot and undershoot:

May damage the chip or cause latch-up

Ringing and glitches:

Affect signal quality and disrupt timing

Timing degradation: Longer signal setup times and insufficient timing margins

Increased bit error rate:

Eye diagram closure and reduced system stability

Increased EMI Radiation:

Reflected energy radiates as electromagnetic waves

The key to resolving impedance mismatch is ensuring impedance continuity. 

From the design stage, one must consciously control trace geometry parameters, plan the stackup rationally, and avoid structures that cause impedance discontinuities. 

Termination resistors are a necessary measure, but they are not a panacea—first get the design right; termination is merely the icing on the cake.

In high-speed design, impedance control is not an option; it is a mandatory requirement. Discovering issues only after the board is manufactured makes corrections extremely difficult.